Introduction

The advancement of quantum computing hinges not only on the design and fabrication of high-quality chips but also on the deployment of precise, stable, and comprehensive testing systems. The Quantum Computing Test Space (QC-Test), developed by Academia Sinica, is dedicated to serving as a core verification hub to unlock the full potential of quantum processors (QPUs). QC-Test focuses on qubit operation, calibration, and error correction, establishing highly efficient and reliable testing and control workflows that span all stages—from initial component evaluation to advanced fault-tolerant quantum computing (FTQC) validation.
At its heart, QC-Test is centered around the QPU, integrated with a dilution refrigerator (DR) that provides an ultra-low-temperature environment far below the cosmic microwave background, effectively shielding against thermal disturbances and radiation. Quantum chips are encased in shielded packaging and connected via high-density, low-noise wiring to precision electronic control modules (DACs, ADCs, FPGAs, etc.), enabling automated calibration and real-time feedback control. This configuration forms a complete quantum computer stack for testing. QC-Test is actively optimizing and automating the calibration process to enhance QPU stability and testing efficiency.
Academia Sinica has invested extensively over the years in both the hardware and software of QC-Test, ensuring it operates at peak performance. Concurrently, it is developing a comprehensive quantum software stack, ranging from low-level control to quantum error correction (QEC) and advanced application algorithms. QC-Test also facilitates horizontal integration with GPUs, enabling efficient execution of quantum-classical hybrid workloads. Beyond a mere testing environment, QC-Test serves as a vital hub for software-hardware integration and technology validation.

Core Mission
．Maximize QPU Performance: Unlock chip potential through accurate testing and meticulous calibration.
．Integrate Software and Hardware: Advance full-stack development from control to application layers.
．Enable Quantum Application Validation: Provide shared infrastructure and technical support to accelerate adoption in academia and industry.
．Support Fundamental Science: Facilitate cutting-edge research with high-quality QPUs designed for foundational studies.

QC-Test Highlights
．Vertical Integration: Encompasses pulse control, readout, QEC, algorithms, and hybrid applications.
．Horizontal Expansion: Integrates with GPU and HPC resources to support hybrid quantum-classical computing.
．Rapid Iteration: Offers immediate testing of locally fabricated quantum chips, enabling a closed-loop development cycle.

QC-Test Services
．Customized QPU Research & Validation: Supports academic and partner institutions in Hamiltonian simulation, chip fabrication (in collaboration with the Quantum Chip Fabrication Platform), and real-sample testing tailored to specific architectures.
．Multilevel QPU Control & Algorithm Testing: Provides access to low-level control software, enabling custom algorithm validation and support for multi-channel pulse control.
．Fault-Tolerant Quantum Computing (FTQC) Experiments: Offers support for implementing and testing error correction codes (e.g., surface code), decoders, and fault-tolerant logical gates.
．Superconducting Quantum Subsystem Testing: Conducts cryogenic testing of subsystem components such as Cryo-CMOS, parametric amplifiers (PAs), and low-noise amplifiers (LNAs), supporting development and integration validation.

Conclusion & Vision
QC-Test is committed to becoming a key shared infrastructure within Taiwan’s quantum computing R&D ecosystem—bridging academia, industry, and public resources to develop world-class testing and validation capabilities. We welcome collaboration from all sectors to jointly accelerate the key innovation and practical realization of quantum advantage.

Contact person:
David Teik-Hui Lee
Assistant Research Scientist
Email: takehuge@as.edu.tw

Regulations

QC-Test Service Policies 

• Online Access(Internal system. Please contact support.): QC-Test is managed and operated by professional staff. Users can log in with authorized accounts for remote access or attend onsite sessions for observation. 
• Resource Scheduling: Tests are scheduled based on the availability of QPUs and DRs. 
• Confidentiality: Both parties must adhere to strict confidentiality protocols to ensure project data security. Intellectual property matters will be negotiated between respective legal departments. 
• Publication Guidelines: Authorship order and acknowledgements must be agreed upon by both parties, based on academic ethics and mutual consent. 

QC-Test Service Workflow 

• Needs Assessment: Contact our scientist with details of expected testing content, QPU specifications, and any special requirements. 
• Scheduling: QC-Test arranges the testing timeline based on available resources; technical review meetings may be held if necessary. 
• Execution & Deliverables: Standardized benchmark results and control parameters are delivered to support downstream analysis and research.